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1 TGC4704-FC november 2009 ? rev a triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com primary applications key features measured performance 38 to 77 ghz doubler and medium power amplifier product description the triquint TGC4704-FC is a flip-chip frequency doubler. it combines an output medium power amplifier and a frequency doubler at frequencies in the automotive radar frequency band. the TGC4704-FC is designed using triquint?s proven 0.13 m phemt process and front-side cu / sn pillar technology for simplified assembly and low interconnect inductance. die reliability is enhanced by using triquint?s bcb polymeric passivation process. the TGC4704-FC typically provides 14 dbm saturated output power with 5 db conversion gain. lead-free and rohs compliant. ? rf output frequency range: 76?77 ghz ? input frequency range: 38.0?38.5 ghz ? two outputs ? out1 (main) and out2 (12 db coupled from out1) ? 14 dbm saturated output power ? 5 db conversion gain ? 50 db input frequency isolation at output ? input return loss > 8 db ? output return loss > 10 db ? bias: vd = 3.75 v, idq = 180 ma, vg1 = -0.4 v vg2 = +0.2 v typical ? technology: 0.13 um phemt with front-side cu/sn pillars ? chip dimensions: 3.38 x 1.37 x 0.38 mm ? automotive radar ? e-band communication bias conditions: vd = 4.0 v, vg1 = -0.4 v, vg2= 0.2 v, idq = 180 ma typical -5 0 5 10 15 -6 -4 -2 0 2 4 6 8 10 12 14 16 input power (dbm) output power at 2 x input freq (dbm) input freq: 38.25 ghz input freq: 38.50 ghz 20 25 30 35 40 45 50 55 60 30 35 40 45 50 55 60 65 70 75 80 85 90 frequency (ghz) isolation (db) -5 0 5 10 15 output power (dbm) fundamental 2x fundamental output @ fund freq - input @ fund freq output @ 2x fund freq ( fund freq:+11 dbm at input)
2 TGC4704-FC november 2009 ? rev a triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com table ii recommended operating conditions table i absolute maximum ratings 1 / symbol parameter value notes vd-vg drain to gate voltage 5.5 v vd drain voltage 4.0 v vg gate voltage range -1 to + 0.45 v id drain current 330 ma ig gate current range -0.5 to +3.0 ma pin input continuous wave power 16 dbm 1 / these ratings represent the maximum operable val ues for this device. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device and / or affect device lifetime. these are stress ratings only, an d functional operation of the device at these conditions is not implied. symbol parameter 1 / value vd drain voltage 3.75 v idq drain current, no rf signal at input 180 ma id drain current, rf signal at input 240 ma vg1 multiplier stage gate voltage -0.4 v vg2a thru vg2d amplifier stages gate voltage +0.2 v 1 / see electrical schematic diagram for bias instruc tions.
3 TGC4704-FC november 2009 ? rev a triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com table iii rf characterization table bias: vd = 3.75 v v, idq = 180 ma, vg1 = -0.4 v, vg2 = +0.2 v typical symbol parameter test conditions minimum nominal units irl input return loss fin = 38.0 ? 38.5 ghz 8 db orl output return loss fin = 76.0 ? 77.0 ghz 10 db pout output power (pin = 8 dbm) fin = 38.5 ghz fout = 77 ghz 11.5 12.5 dbm pout output power (pin = 10 dbm) fin = 38.5 ghz fout = 77 ghz 13.0 14.0 dbm isol isolation fin = 38.0 ? 38.5 ghz fout = 38.0 ? 38.5 ghz 50 db
4 TGC4704-FC november 2009 ? rev a triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com table iv power dissipation and thermal properties 1 / for a median life of 2.4e+7 hours, power dissipat ion is limited to pd(max) = (150 c ? tbase c)/ jc. 2 / channel operating temperature will directly affect the device median time to failure (mttf). for maximum life, it is recommended that channel temper atures be maintained at the lowest possible levels. 3 / for this flip-chip die, the baseplate is a plane between the cu/sn pillars and the test board . for the TGC4704-FC, the critical pillars for thermal power dissipation are 24 thru 33. (see mechanical drawing.) parameter test conditions value notes maximum power dissipation tbaseplate = 128.8 c pd = 1.2 w tchannel = 150 c tm = 2.4e+7 hrs 1 / 2 / 3 / thermal resistance, jc vd = 4.0 v vg1 = -0.4 v vg2 = +0.2 v id = 0.240 a pd = 0.960 w tbaseplate = 85 c jc = 17.7 (c/w) tchannel = 102 c tm = 9.8e+9 hrs 3 / mounting temperature refer to solder reflow profiles (pp 12) storage temperature -65 to 150 c median lifetime (tm) vs channel temperature 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 1.e+09 1.e+10 1.e+11 1.e+12 1.e+13 25 50 75 100 125 150 175 200 channel temperature (c) median lifetime (hours) fet11
5 TGC4704-FC november 2009 ? rev a triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com -5 0 5 10 15 -6 -4 -2 0 2 4 6 8 10 12 14 16 input power (dbm) output power at 2 x input freq (dbm) input freq: 38.25 ghz input freq: 38.50 ghz 20 25 30 35 40 45 50 55 60 33 34 35 36 37 38 39 40 41 42 43 frequency (ghz) isolation (db) output @ fund freq - input @ fund freq measured data on flipped die on carrier board bias: vd = 4.0 v, idq = 180 ma, vg1 = -0.4 v, vg2 = +0.2 v typical
6 TGC4704-FC november 2009 ? rev a triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com -5 0 5 10 15 74 75 76 77 78 79 80 81 82 83 frequency (ghz) output power (dbm) output @ 2x fund freq ( fund freq:+11 dbm at input) -5 0 5 10 -6 -4 -2 0 2 4 6 8 10 12 14 16 input power (dbm) conversion gain (db) input freq: 38.25 ghz input freq: 38.50 ghz measured data on flipped die on carrier board bias: vd = 4.0 v, idq = 180 ma, vg1 = -0.4 v, vg2 = +0.2 v typical
7 TGC4704-FC november 2009 ? rev a triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com -16 -14 -12 -10 -8 -6 -4 -2 0 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 frequency (ghz) irl, orl (db) irl orl 0 2 4 6 8 10 12 14 16 72 74 76 78 80 82 84 output frequency (ghz) coupling factor - rf out1 to rf out2 (db) measured data on flipped die on carrier board bias: vd = 4.0 v, idq = 180 ma, vg1 = -0.4 v, vg2 = +0.2 v typical
8 TGC4704-FC november 2009 ? rev a triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com 180 200 220 240 260 280 -6 -4 -2 0 2 4 6 8 10 12 14 16 input power (dbm) drain current (ma) input freq: 38.25 ghz input freq: 38.50 ghz 180 200 220 240 260 280 72 74 76 78 80 82 84 frequency (ghz) drain current (ma) output @ 2x fund freq ( fund freq:+11 dbm at input) measured data on flipped die on carrier board bias: vd = 4.0 v, idq = 180 ma, vg1 = -0.4 v, vg2 = +0.2 v typical
9 TGC4704-FC november 2009 ? rev a triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com electrical schematic bias procedures bias-up procedure bias-down procedure vg1, vg2 set to -0.4 v turn off rf signal to input vd set to +3.75 v reduce vg1,2 to -0.4 v. ensure id ~ 0 ma adjust vg2 only more positive until id is 180 ma (vg ~ +0.2 v) turn vd to 0 v apply rf signal to input id will be ~240 ma (14) (23) rf in (22) rf out1 (10) gnd (plr 1,3, 8,19) (9) TGC4704-FC rf out2 (13) vd 100 pf vg1 vg2 100 pf 100 pf (2) (4) (5) (6) (7) (18) (17) (16) (15) (20) (24 & 29) (25 & 30) (26 & 31) (27 & 32) (28 & 33) (21) (12) (11)
10 TGC4704-FC november 2009 ? rev a triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com gaas mmic devices are susceptible to damage from el ectrostatic discharge. proper precautions should be observed during handling, assembly and test. mechanical drawing drawing is for chip face-up units: millimeters thickness: 0.380 die x, y size tolerance +/- 0.050 chip edge to pillar dimensions are shown to center of pillar pillar #22 rf in 0.075 ? pillar #10 rf out1 (main) 0.075 ? pillar #13 rf out2 (coupled) 0.075 ? pillar #9, 11, 12, 14, 21, 23 rf cpw ground 0.075 ? pillar #20 vg1 0.075 ? pillar #18 vg2a 0.075 ? pillar #17 vg2b 0.075 ? pillar #16 vg2c 0.075 ? pillar #15 vg2d 0.075 ? pillar #2 vd1 0.075 ? pillar #4 vd2a 0.075 ? pillar #5 vd2b 0.075 ? pillar #6 vd2c 0.075 ? pillar #7 vd2d 0.075 ? pillar #1,3 8,19, 24 thru 33 dc ground 0.075 ? 2.227 2.304 2.537 2.730 2.780 3.005 3.230 0.381 0.458 0.683 0.908 1.308 1.559 1.922 2.302 2.685 2.964 3.380 0.651 0.124 0.376 0.834 0.834 1 2 5 3 4 6 7 8 22226 25 27 28 9 17 31 20 30 18 32 33 15 11 14 29 24 10 21 22 23 16 13 12 19 0.126 0.587 0.778 1.244 0.457 0.682 0.907 0.000 0.000 1.549 1.924 1.308 1.554 1.916 3.257 1.370
11 TGC4704-FC november 2009 ? rev a triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com gaas mmic devices are susceptible to damage from el ectrostatic discharge. proper precautions should be observed during handling, assembly and test. recommended assembly diagram die is flip-chip soldered to a 15 mil thick alumina test substrate TGC4704-FC die (flip-chip bonded) 100 pf vg1 vg2 100 pf vd gnd gnd gnd gnd 100 pf rf in rf out1 (main) rf out2 (coupled) TGC4704-FC data represented in this datasheet was taken using co- planar waveguide (cpw) transition on the substrate and ground-signal- ground probes TGC4704-FC die
12 TGC4704-FC november 2009 ? rev a triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com gaas mmic devices are susceptible to damage from el ectrostatic discharge. proper precautions should be observed during handling, assembly and test. assembly notes ordering information part package style TGC4704-FC gaas mmic die process sn reflow ramp-up rate 3 0 c/sec flux activation time and temperature 60 ? 120 sec @ 1 40 ? 160 0 c time above melting point (245 0 c) 60 ? 150 sec max peak temperature 300 0 c time within 5 0 c of peak temperature 10 ? 20 sec ramp-down rate 4 ? 6 0 c/sec typical reflow profiles for triquint cu / sn pillars component placement and die attach assembly notes: ? vacuum pencils and/or vacuum collets are the prefe rred method of pick up. ? air bridges must be avoided during placement. ? cu pillars on die are 65 um tall with a 22 um tall sn solder cap. ? recommended board metallization is evaporated tiw f ollowed by nickel/gold at pillar attach interface. ni is the adhesion layer for the solder and the gold keeps the ni from oxidizing . the au should be kept to a minimum to avoid embri ttlement; suggested au / sn mass ratio must not exceed 8%. ? au metallization is not recommended on traces due to solder wicking and consumption concerns. if au traces are used, a physical solder barrier must be applied or designed into the pad area of the board. the barrier must be suffici ent to keep the solder from undercutting the barrier. reflow process assembly notes: ? minimum alloying temperatures 245 0 c. ? repeating reflow cycles is not recommended due to sn consumption on the first reflow cycle. ? an alloy station or conveyor furnace with an inert atmosphere such as n2 should be used. ? dip copper pillars in ?no-clean flip chip? flux pri or to solder attach. suggest using a high temperatu re flux. avoid exposing entire die to flux. ? if screen printing flux, use small apertures and m inimize volume of flux applied. ? coefficient of thermal expansion matching between the mmic and the substrate/board is critical for lo ng-term reliability. ? devices must be stored in a dry nitrogen atmospher e. ? suggested reflow will depend on board material and density.

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